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ABRIDGED DATA SHEET
Rev 0: 6/10
1-Wire SHA-1 Authenticated 1Kb EEPROM with 1.8V Operation
General Description
The DS28E02 combines 1024 bits of EEPROM with challenge-and-response authentication security implemented with the FIPS 180-3 Secure Hash Algorithm (SHA-1). The 1024-bit EEPROM array is configured as four pages of 256 bits with a 64-bit scratchpad to perform write operations. All memory pages can be write protected, and one page can be put in EPROM-emulation mode, where bits can only be changed from a 1 to a 0 state. Each DS28E02 has its own guaranteed unique 64-bit ROM registration number that is factory installed into the chip. The DS28E02 communicates over the single-contact 1-Wire(R) bus. The communication follows the standard 1-Wire protocol with the registration number acting as the node address in the case of a multidevice 1-Wire network.
Features
1024 Bits of EEPROM Memory Partitioned Into Four Pages of 256 Bits On-Chip 512-Bit SHA-1 Engine to Compute 160Bit Message Authentication Codes (MACs) and to Generate Secrets Write Access Requires Knowledge of the Secret and the Capability of Computing and Transmitting a 160-Bit MAC as Authorization User-Programmable Page Write Protection for Page 0, Page 3, or All Four Pages Together User-Programmable OTP EPROM Emulation Mode for Page 1 ("Write to 0") Communicates to Host with a Single Digital Signal at 12.5kbps or 35.7kbps Using 1-Wire Protocol Switchpoint Hysteresis and Filtering to Optimize Communication Performance in the Presence of Noise Reads and Writes Over 1.75V to 3.65V Voltage Range from -20C to +85C 6-Lead TSOC and TDFN Packages
DS28E02
Applications
Reference Design License Management System Intellectual Property Protection Sensor/Accessory Authentication and Calibration Medical Consumable Authentication Printer Cartridge Configuration and Monitoring
Typical Operating Circuit
PART
VCC RPUP IO C DS28E02
Ordering Information
TEMP RANGE -20C to +85C -20C to +85C -20C to +85C PIN-PACKAGE 6 TSOC 6 TSOC 6 TDFN-EP* (2.5k pcs) DS28E02P+ DS28E02P+T&R DS28E02Q+T&R
+Denotes a lead(Pb)-free/RoHS-compliant package. T&R = Tape and reel. *EP = Exposed pad.
GND
1-Wire is a registered trademark of Maxim Integrated Products, Inc.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
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1-Wire SHA-1 Authenticated 1Kb EEPROM with 1.8V Operation DS28E02
ABSOLUTE MAXIMUM RATINGS
IO Voltage Range to GND .......................................-0.5V to +4V IO Sink Current ...................................................................20mA Operating Temperature Range ...........................-20C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-55C to +125C Lead Temperature (soldering, 10s) .................................+300C Soldering Temperature (reflow) .......................................+260C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(TA = -20C to +85C.) (Note 1)
PARAMETER IO PIN: GENERAL DATA 1-Wire Pullup Voltage 1-Wire Pullup Resistance Input Capacitance Input Load Current High-to-Low Switching Threshold Input Low Voltage Low-to-High Switching Threshold Switching Hysteresis Output Low Voltage SYMBOL VPUP RPUP CIO IL VTL VIL VTH VHY VOL (Note 2) (Notes 2, 3) (Notes 4, 5) IO pin at VPUP (Notes 5, 6, 7) (Notes 2, 8) (Notes 5, 6, 9) 0.74 0.26 20 20 80 28 480 50 480 48 60 7 60 8 1 1 5 1 tRL + tRL + 640 80 CONDITIONS MIN 1.75 300 1500 0.05 0.4 5 VPUP - 0.89 0.30 VPUP - 0.49 1.02 0.4 TYP MAX 3.65 750 UNITS V pF A V V V V V s s
(Notes 5, 6, 10) At 4mA current load (Note 11) Standard speed, RPUP = 750 Recovery Time (Notes 2, 12) tREC Overdrive speed Standard speed Time Slot Duration (Notes 2, 13) tSLOT Overdrive speed IO PIN: 1-Wire RESET, PRESENCE-DETECT CYCLE Standard speed Reset Low Time (Note 2) tRSTL Overdrive speed Standard speed Reset High Time (Note 14) tRSTH Overdrive speed Standard speed Presence-Detect Sample Time tMSP (Notes 2, 15) Overdrive speed IO PIN: 1-Wire WRITE Standard speed Write-Zero Low Time (Notes 2, 16) tW0L Overdrive speed Standard speed Write-One Low Time (Notes 2, 16) tW1L Overdrive speed IO PIN: 1-Wire READ Standard speed Read Low Time (Notes 2, 17) tRL Overdrive speed Standard speed Read Sample Time (Notes 2, 17) tMSR Overdrive speed EEPROM IO voltage < 3.65V Programming Current I PROG IO voltage < 2.95V (Notes 5, 18) IO voltage = 1.75V
s s
72 10 120 15.5 15 2 15 215 2 3.5 2.5 1.0
s
s s
s s
mA
2
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1-Wire SHA-1 Authenticated 1Kb EEPROM with 1.8V Operation
ELECTRICAL CHARACTERISTICS (continued)
(TA = -20C to +85C.) (Note 1)
PARAMETER Programming Time Write/Erase Cycles (Endurance) (Notes 20, 21) Data Retention (Notes 22, 23, 24) SHA-1 ENGINE Computation Current Computation Time (Notes 5, 25) SYMBOL t PROG NCY tDR ILCSHA tCSHA (Note 19) At +25C At +85C At +85C (Notes 5, 18) CONDITIONS MIN 200,000 50,000 40 TYP MAX 25 UNITS ms -- Years mA ms
DS28E02
Refer to full data sheet
Note 1: Note 2: Note 3: Note 4: Note 5: Note 6:
Note 7: Note 8: Note 9: Note 10: Note 11: Note 12: Note 13: Note 14: Note 15: Note 16: Note 17: Note 18:
Specifications at TA = -20C are guaranteed by design only and not production tested. System requirement. Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times. The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. Maximum value represents the internal parasite capacitance when VPUP is first applied. If a 750 pullup resistor is used, the parasite capacitance does not affect normal communications 2s after VPUP has been applied. Guaranteed by design, characterization, and/or simulation only. Not production tested. VTL, VTH, and VHY are a function of the internal supply voltage, which is a function of VPUP, RPUP, 1-Wire timing, and capacitive loading on IO. Lower VPUP, higher RPUP, shorter tREC, and heavier capacitive loading all lead to lower values of VTL, VTH, and VHY. Voltage below which, during a falling edge on IO, a logic 0 is detected. The voltage on IO must be less than or equal to VILMAX at all times the master is driving IO to a logic 0 level. Voltage above which, during a rising edge on IO, a logic 1 is detected. After VTH is crossed during a rising edge on IO, the voltage on IO must drop by at least VHY to be detected as logic 0. The I-V characteristic is linear for voltages less than 1V. Applies to a single device attached to a 1-Wire line. Defines maximum possible bit rate. Equal to 1/(tW0LMIN + tRECMIN). An additional reset or communication sequence cannot begin until the reset high time has expired. Interval after tRSTL during which a bus master is guaranteed to sample a logic 0 on IO if there is a DS28E02 present. in Figure 12 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to VTH. The actual maximum duration for the master to pull the line low is tW1LMAX + tF - and tW0LMAX + tF - , respectively. in Figure 12 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to the input-high threshold of the bus master. The actual maximum duration for the master to pull the line low is tRLMAX + tF. Current drawn from IO during the EEPROM programming interval or SHA-1 computation.
Note 19: Refer to full data sheet for this note.
Note 20: Note 21: Note 22: Note 23:
Write-cycle endurance is degraded as TA increases. Not 100% production tested; guaranteed by reliability monitor sampling. Data retention is degraded as TA increases. Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to the data sheet limit at operating temperature range is established by reliability testing. Note 24: EEPROM writes can become nonfunctional after the data-retention time is exceeded. Long-term storage at elevated temperatures is not recommended; the device can lose its write capability after 10 years at +125C or 40 years at +85C. Note 25: Refer to full data sheet for this note.
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1-Wire SHA-1 Authenticated 1Kb EEPROM with 1.8V Operation DS28E02
Pin Configurations
TOP VIEW TOP VIEW
+
DS28E02 GND IO N.C. 1 2 3 DS28E02 6 N.C. N.C. 5 4 N.C. 2802 ymrrF N.C. IO 2 5 N.C. 1
+
6 N.C.
TSOC
GND
3
EP
4
N.C.
TDFN (3mm x 3mm)
Pin Description
PIN TSOC 1 2 3, 4, 5, 6 -- TDFN-EP 3 2 1, 4, 5, 6 EP NAME GND IO N.C. EP Ground Reference 1-Wire Bus Interface. Open-drain signal that requires an external pullup resistor. Not Connected Exposed Pad. Solder evenly to the board's ground plane for proper operation. Refer to Application Note 3273: Exposed Pads: A Brief Introduction for additional information. FUNCTION
Detailed Description
The DS28E02 combines 1024 bits of EEPROM organized as four 256-bit pages, a 64-bit secret, a register page, a 512-bit SHA-1 engine, and a 64-bit ROM registration number in a single chip. Data is transferred serially through the 1-Wire protocol, which requires only a single data lead and a ground return. The DS28E02 has an additional memory area called the scratchpad that acts as a buffer when writing to the memory, the register page, or when installing a new secret. Data is first written to the scratchpad from where it can be read back. After the data has been verified, a copy scratchpad command transfers the data to its final memory location, provided that the DS28E02 receives a matching 160-bit MAC. The computation of the MAC involves the secret and additional data stored in the DS28E02 including the device's registration number. The
DS28E02 understands a unique command "Refresh Scratchpad." Proper use of a refresh sequence after a copy scratchpad operation reduces the number of weak bit failures if the device is used in a touch environment (see the Writing with Verification section). The refresh sequence also provides a means to restore functionality in a device with bits in a weak state. In addition to its important use as a unique data value in cryptographic SHA-1 computations, the device's 64-bit ROM ID guarantees unique identification and can be used to electronically identify the equipment in which it is used. The ROM ID is also used to address the device for the case of a multidrop 1-Wire network environment, where multiple devices reside on a common 1-Wire bus and operate independently of each other. Applications of the DS28E02 include reference design license management, system intellectual property protection, accessory
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1-Wire SHA-1 Authenticated 1Kb EEPROM with 1.8V Operation DS28E02
PARASITE POWER
1-Wire NET 1-Wire FUNCTION CONTROL 64-BIT ROM
MEMORY AND SHA-1 FUNCTION CONTROL UNIT
512-BIT SECURE HASH ALGORITHM ENGINE
DS28E02
CRC16 GENERATOR 64-BIT SCRATCHPAD DATA MEMORY 4 PAGES OF 256 BITS EACH
REGISTER PAGE
Figure 1. Block Diagram
or consumable authentication and calibration, and printer cartridge configuration and monitoring.
Overview
The block diagram in Figure 1 shows the relationships between the major control and memory sections of the DS28E02. The DS28E02 has six main data components: 64-bit ROM, 64-bit scratchpad, four 256-bit pages of EEPROM, register page, and a 512-bit SHA-1 engine. Figure 2 shows the hierarchic structure of the 1-Wire protocol. The bus master must first provide one of the seven ROM function commands: Read ROM, Match ROM, Search ROM, Skip ROM, Resume Communication, Overdrive-Skip ROM, or OverdriveMatch ROM. Upon completion of an Overdrive-Skip ROM or Overdrive-Match ROM command executed at standard speed, the device enters overdrive mode where all subsequent communication occurs at a higher
speed. The protocol required for these ROM function commands is described in Figure 10. After a ROM function command is successfully executed, the memory and SHA-1 functions become accessible and the master can provide any one of the 9 available function commands. The function protocols are described in Figure 8. All data is read and written least significant bit first.
64-Bit ROM
Each DS28E02 contains a unique ROM registration number that is 64 bits long. The first 8 bits are a 1-Wire family code. The next 48 bits are a unique serial number. The last 8 bits are a cyclic redundancy check (CRC) of the first 56 bits. See Figure 3 for details. The 1-Wire CRC is generated using a polynomial generator consisting of a shift register and XOR gates as shown in Figure 4. The polynomial is X8 + X5 + X4 + 1. Additional information about the 1-Wire CRC is available in Application Note
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1-Wire SHA-1 Authenticated 1Kb EEPROM with 1.8V Operation DS28E02
DS28E02 COMMAND LEVEL: AVAILABLE COMMANDS: READ ROM MATCH ROM SEARCH ROM SKIP ROM RESUME OVERDRIVE-SKIP ROM OVERDRIVE-MATCH ROM DATA FIELD AFFECTED: 64-BIT REG. #, RC-FLAG 64-BIT REG. #, RC-FLAG 64-BIT REG. #, RC-FLAG RC-FLAG RC-FLAG RC-FLAG, OD-FLAG 64-BIT REG.#, RC-FLAG, OD-FLAG
1-Wire ROM FUNCTION COMMANDS (SEE FIGURE 10)
DEVICE-SPECIFIC MEMORY FUNCTION COMMANDS (SEE FIGURE 8)
Refer to the full data sheet.
Figure 2. Hierarchic Structure for 1-Wire Protocol
MSB 8-BIT CRC CODE MSB LSB MSB 48-BIT SERIAL NUMBER LSB MSB 8-BIT FAMILY CODE
LSB
LSB
Figure 3. 64-Bit ROM
POLYNOMIAL = X8 + X5 + X4 + 1
1ST STAGE X0 X1
2ND STAGE X2
3RD STAGE X3
4TH STAGE X4
5TH STAGE X5
6TH STAGE X6
7TH STAGE X7
8TH STAGE X8
INPUT DATA
Figure 4. 1-Wire CRC Generator
27: Understanding and Using Cyclic Redundancy Checks with Maxim iButton Products. The shift register bits are initialized to 0. Then, starting with the least significant bit of the family code, one bit at a time is shifted in. After the 8th bit of the family code has been entered, the serial number is entered. After the 48th bit of the serial number has been entered, the shift register contains the CRC value. Shifting in the 8 bits of the CRC returns the shift register to all 0s.
Memory Access
The DS28E02 has four memory areas: data memory, secrets memory, register page with special function registers and user bytes, and a volatile scratchpad. The data memory is organized as four pages of 32 bytes.
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1-Wire SHA-1 Authenticated 1Kb EEPROM with 1.8V Operation DS28E02
Refer to the full data sheet.
Figure 5. Memory Map
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1-Wire SHA-1 Authenticated 1Kb EEPROM with 1.8V Operation DS28E02
Refer to the full data sheet.
Figure 6. Memory Protection Matrix
BIT # TARGET ADDRESS (TA1) 7 T7 6 T6 5 T5 4 T4 3 T3 2 T2 (0) 1 T1 (0) 0 T0 (0)
TARGET ADDRESS (TA2)
T15
T14
T13
T12
T11
T10
T9
T8
ENDING ADDRESS WITH DATA STATUS (E/S) (READ ONLY)
AA
1
PF
1
1
E2 (1)
E1 (1)
E0 (1)
Figure 7. Address Registers
Address Registers and Transfer Status
The DS28E02 employs three address registers: TA1, TA2, and E/S (Figure 7). These registers are common to many other 1-Wire devices, but operate slightly differently with the DS28E02. Registers TA1 and TA2 must be loaded with the target address to which the data is written or from which data is read. Register E/S is a readonly transfer-status register used to verify data integrity with write commands. Since the scratchpad of the DS28E02 is designed to accept data in blocks of 8 bytes only, the lower 3 bits of TA1 are forced to 0 and
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1-Wire SHA-1 Authenticated 1Kb EEPROM with 1.8V Operation
the lower 3 bits of the E/S register (ending offset) always read 1. This indicates that all the data in the scratchpad is used for a subsequent copying into main memory or secret. Bit 5 of the E/S register, called PF or partial byte flag, is a logic 1 if the number of data bits sent by the master is not an integer multiple of eight or if the data in the scratchpad is not valid due to a loss of power. A valid write to the scratchpad clears the PF bit. Bits 3, 4, and 6 have no function; they always read 1. The partial flag supports the master checking the data integrity after a write command. The highest valued bit of the E/S register, called authorization accepted (AA), acts as a flag to indicate that the data stored in the scratchpad has already been copied to the target memory address. Writing data to the scratchpad clears this flag. scratchpad command, target address, E/S register, and scratchpad data follows the scratchpad data. As with the write scratchpad command, this CRC can be compared to the value the master has calculated to determine if the communication was successful. After the master has verified the data, it can send the copy scratchpad to copy the scratchpad to memory.
DS28E02
Writing with Verification
To write data to the DS28E02, the scratchpad must be used as intermediate storage. First, the master issues the Write Scratchpad command, which specifies the desired target address and the data to be written to the scratchpad. Note that writes to data memory must be performed on 8-byte boundaries with the three LSBs of the target address T[2:0] equal to 000b. Therefore, if T[2:0] are sent with nonzero values, the device sets these bits to 0 and uses the modified address as the target address. The master should always send eight complete data bytes. After the 8 bytes of data have been transmitted, the master can elect to receive an inverted CRC-16 of the Write Scratchpad command, the address as sent by the master, and the data as sent by the master. The master can compare the CRC to the value it has calculated itself to determine if the communication was successful. After the scratchpad has been written, the master should always perform a read scratchpad to verify that the intended data was in fact written. During a read scratchpad, the DS28E02 repeats the target address TA1 and TA2 and sends the contents of the E/S register. The partial flag (bit 5 of the E/S register) is set to 1 if the last data byte the DS28E02 received during a write scratchpad or refresh scratchpad command was incomplete, or if there was a loss of power since data was last written to the scratchpad. The authorization-accepted (AA) flag (bit 7 of the E/S register) is normally cleared by a write scratchpad or refresh scratchpad; therefore, if it is set to 1, it indicates that the DS28E02 did not understand the proceeding write (or refresh) scratchpad command. In either of these cases, the master should rewrite the scratchpad. After the master receives the E/S register, the scratchpad data is received. The descriptions of write scratchpad and refresh scratchpad provide clarification of what changes can occur to the scratchpad data under certain conditions. An inverted CRC of the read
Refer to the full data sheet for more information on Writing Refer to the full data sheet. with Verification.
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1-Wire SHA-1 Authenticated 1Kb EEPROM with 1.8V Operation DS28E02
Memory and SHA-1 Function Commands
This section describes the commands and flowcharts needed to use the memory and SHA-1 engine of the device. Refer to the full data sheet for more information.
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1-Wire SHA-1 Authenticated 1Kb EEPROM with 1.8V Operation DS28E02
1-Wire Bus System
The 1-Wire bus is a system that has a single bus master and one or more slaves. In all instances the DS28E02 is a slave device. The bus master is typically a microcontroller. The discussion of this bus system is broken down into three topics: hardware configuration, transaction sequence, and 1-Wire signaling (signal types and timing). The 1-Wire protocol defines bus transactions in terms of the bus state during specific time slots, which are initiated on the falling edge of sync pulses from the bus master.
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1-Wire SHA-1 Authenticated 1Kb EEPROM with 1.8V Operation DS28E02
VPUP BUS MASTER RPUP Rx DATA Rx DS28E02 1-Wire PORT
Tx
Rx = RECEIVE Tx = TRANSMIT OPEN-DRAIN PORT PIN
IL
Tx
100 MOSFET
Figure 9. Hardware Configuration
Hardware Configuration
The 1-Wire bus has only a single line by definition; it is important that each device on the bus be able to drive it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have open-drain or three-state outputs. The 1-Wire port of the DS28E02 is open drain with an internal circuit equivalent to that shown in Figure 9. A multidrop bus consists of a 1-Wire bus with multiple slaves attached. The DS28E02 supports both a standard and overdrive communication speed of 12.5kbps (max) and 35.7kbps (max), respectively. Note that legacy 1-Wire products support a standard communication speed of 16.3kbps and overdrive of 142kbps. The value of the pullup resistor primarily depends on the network size and load conditions. The DS28E02 requires a pullup resistor of 750 (max) at any speed.
The idle state for the 1-Wire bus is high. If for any reason a transaction needs to be suspended, the bus must be left in the idle state if the transaction is to resume. If this does not occur and the bus is left low for more than 16s (overdrive speed) or more than 120s (standard speed), one or more devices on the bus could be reset.
Transaction Sequence
The protocol for accessing the DS28E02 through the 1-Wire port is as follows: * Initialization * ROM Function Command * Memory/SHA Function Command * Transaction/Data
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1-Wire SHA-1 Authenticated 1Kb EEPROM with 1.8V Operation DS28E02
Initialization
All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the slave(s). The presence pulse lets the bus master know that the DS28E02 is on the bus and is ready to operate. For more details, see the 1-Wire Signaling section.
Search ROM [F0h]
When a system is initially brought up, the bus master might not know the number of devices on the 1-Wire bus or their registration numbers. By taking advantage of the wired-AND property of the bus, the master can use a process of elimination to identify the registration numbers of all slave devices. For each bit of the registration number, starting with the least significant bit, the bus master issues a triplet of time slots. On the first slot, each slave device participating in the search outputs the true value of its registration number bit. On the second slot, each slave device participating in the search outputs the complemented value of its registration number bit. On the third slot, the master writes the true value of the bit to be selected. All slave devices that do not match the bit written by the master stop participating in the search. If both of the read bits are zero, the master knows that slave devices exist with both states of the bit. By choosing which state to write, the bus master branches in the search tree. After one complete pass, the bus master knows the registration number of a single device. Additional passes identify the registration numbers of the remaining devices. Refer to Application Note 187: 1-Wire Search Algorithm for a detailed discussion, including an example.
1-Wire ROM Function Commands
Once the bus master has detected a presence, it can issue one of the seven ROM function commands that the DS28E02 supports. All ROM function commands are 8 bits long. A list of these commands follows (see the flowchart in Figure 10).
Read ROM [33h]
The Read ROM command allows the bus master to read the DS28E02's 8-bit family code, unique 48-bit serial number, and 8-bit CRC. This command can only be used if there is a single slave on the bus. If more than one slave is present on the bus, a data collision occurs when all slaves try to transmit at the same time (open drain produces a wired-AND result). The resultant family code and 48-bit serial number result in a mismatch of the CRC.
Skip ROM [CCh]
This command can save time in a single-drop bus system by allowing the bus master to access the memory functions without providing the 64-bit registration number. If more than one slave is present on the bus and, for example, a read command is issued following the Skip ROM command, data collision occurs on the bus as multiple slaves transmit simultaneously (open-drain pulldowns produce a wired-AND result).
Match ROM [55h]
The Match ROM command, followed by a 64-bit device registration number, allows the bus master to address a specific DS28E02 on a multidrop bus. Only the DS28E02 that exactly matches the 64-bit registration number responds to the subsequent memory or SHA-1 function command. All other slaves wait for a reset pulse. This command can be used with a single device or multiple devices on the bus.
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1-Wire SHA-1 Authenticated 1Kb EEPROM with 1.8V Operation DS28E02
BUS MASTER Tx RESET PULSE FROM MEMORY AND SHA-1 FUNCTION FLOWCHART (FIGURE 8) OD RESET PULSE? FROM FIGURE 10b
N
OD = 0
Y BUS MASTER Tx ROM FUNCTION COMMAND DS28E02 Tx PRESENCE PULSE
33h READ ROM COMMAND? Y RC = 0
N
55h MATCH ROM COMMAND? Y RC = 0
N
F0h SEARCH ROM COMMAND? Y RC = 0
N
CCh SKIP ROM COMMAND? Y RC = 0
N TO FIGURE 10b
DS28E02 Tx FAMILY CODE (1 BYTE)
DS28E02 Tx BIT 0 MASTER Tx BIT 0 DS28E02 Tx BIT 0 MASTER Tx BIT 0
BIT 0 MATCH?
N
N
BIT 0 MATCH?
Y DS28E02 Tx SERIAL NUMBER, USER-DEFINED FIELD, AND CUSTOM ID (6 BYTES)
Y DS28E02 Tx BIT 1
MASTER Tx BIT 1
DS28E02 Tx BIT 1 MASTER Tx BIT 1
BIT 1 MATCH?
N
N
BIT 1 MATCH? Y DS28E02 Tx BIT 63
Y
DS28E02 Tx CRC BYTE
MASTER Tx BIT 63
DS28E02 Tx BIT 63 MASTER Tx BIT 63
BIT 63 MATCH?
N
N
BIT 63 MATCH?
Y RC = 1
Y RC = 1
TO FIGURE 10b
FROM FIGURE 10b TO MEMORY AND SHA-1 FUNCTION FLOWCHART (FIGURE 8)
Figure 10a. ROM Functions Flowchart
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1-Wire SHA-1 Authenticated 1Kb EEPROM with 1.8V Operation DS28E02
TO FIGURE 10a
FROM FIGURE 10a
A5h RESUME COMMAND? Y
N
3Ch OVERDRIVESKIP ROM? Y RC = 0; OD = 1
N
69h OVERDRIVEMATCH ROM? Y RC = 0; OD = 1
N
RC = 1?
N
Y
MASTER Tx RESET? N
Y
MASTER Tx BIT 0
(SEE NOTE) MASTER Tx RESET? N Y BIT 0 MATCH? N OD = 0
Y
MASTER Tx BIT 1
(SEE NOTE) BIT 1 MATCH? N OD = 0
Y
MASTER Tx BIT 63
(SEE NOTE) BIT 63 MATCH? N OD = 0
Y RC = 1
FROM FIGURE 10a
TO FIGURE 10a
NOTE: THE OD FLAG REMAINS AT 1 IF THE DEVICE WAS ALREADY AT OVERDRIVE SPEED BEFORE THE OVERDRIVE-MATCH ROM COMMAND WAS ISSUED.
Figure 10b. ROM Functions Flowchart
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1-Wire SHA-1 Authenticated 1Kb EEPROM with 1.8V Operation
Resume [A5h]
To maximize the data throughput in a multidrop environment, the Resume command is available. This command checks the status of the RC bit and, if it is set, directly transfers control to the memory and SHA-1 function commands, similar to a Skip ROM command. The only way to set the RC bit is through successfully executing the Match ROM, Search ROM, or Overdrive-Match ROM command. Once the RC bit is set, the device can repeatedly be accessed through the Resume command. Accessing another device on the bus clears the RC bit, preventing two or more devices from simultaneously responding to the Resume command.
Overdrive-Match ROM [69h]
The Overdrive-Match ROM command followed by a 64bit registration number transmitted at overdrive speed allows the bus master to address a specific DS28E02 on a multidrop bus and to simultaneously set it in overdrive mode. Only the DS28E02 that exactly matches the 64bit number responds to the subsequent memory or SHA-1 function command. Slaves already in overdrive mode from a previous Overdrive-Skip ROM or successful Overdrive-Match ROM command remain in overdrive mode. All overdrive-capable slaves return to standard speed at the next reset pulse of minimum 480s duration. The Overdrive-Match ROM command can be used with a single device or multiple devices on the bus.
DS28E02
Overdrive-Skip ROM [3Ch]
On a single-drop bus this command can save time by allowing the bus master to access the memory functions without providing the 64-bit registration number. Unlike the normal Skip ROM command, the OverdriveSkip ROM command sets the DS28E02 into the overdrive mode (OD = 1). All communication following this command must occur at overdrive speed until a reset pulse of minimum 480Is duration resets all devices on the bus to standard speed (OD = 0). When issued on a multidrop bus, this command sets all overdrive-supporting devices into overdrive mode. To subsequently address a specific overdrive-supporting device, a reset pulse at overdrive speed must be issued followed by a Match ROM or Search ROM command sequence. This speeds up the time for the search process. If more than one slave supporting overdrive is present on the bus and the Overdrive-Skip ROM command is followed by a read command, data collision occurs on the bus as multiple slaves transmit simultaneously (open-drain pulldowns produce a wiredAND result).
MASTER Tx "RESET PULSE" VPUP VIHMASTER VTH VTL VILMAX 0V tRSTL tF
1-Wire Signaling
The DS28E02 requires strict protocols to ensure data integrity. The protocol consists of four types of signaling on one line: reset sequence with reset pulse and presence pulse, write-zero, write-one, and read-data. Except for the presence pulse, the bus master initiates all falling edges. The DS28E02 can communicate at at two different speeds: standard speed and overdrive speed. If not explicitly set into the overdrive mode, the DS28E02 communicates at standard speed. While in overdrive mode, the fast timing applies to all waveforms. To get from idle to active, the voltage on the 1-Wire line needs to fall from VPUP below the threshold VTL. To get from active to idle, the voltage needs to rise from VILMAX past the threshold VTH. The time it takes for the voltage to make this rise is seen in Figure 11 as , and its duration depends on the pullup resistor (RPUP) used and the capacitance of the 1-Wire network attached. The voltage VILMAX is relevant for the DS28E02 when determining a logical level, not triggering any events.
MASTER Rx "PRESENCE PULSE" tMSP
tREC tRSTH
RESISTOR
MASTER
DS28E02
Figure 11. Initialization Procedure: Reset and Presence Pulse
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1-Wire SHA-1 Authenticated 1Kb EEPROM with 1.8V Operation
Figure 11 shows the initialization sequence required to begin any communication with the DS28E02. A reset pulse followed by a presence pulse indicates that the DS28E02 is ready to receive data, given the correct ROM and memory and SHA-1 function command. If the bus master uses slew-rate control on the falling edge, it must pull down the line for tRSTL + tF to compensate for the edge. A tRSTL duration of 480s or longer exits the overdrive mode, returning the device to standard speed. If the DS28E02 is in overdrive mode and tRSTL is no longer than 80s, the device remains in overdrive mode. If the device is in overdrive mode and tRSTL is between 80s and 480s, the device resets, but the communication speed is undetermined. After the bus master has released the line it goes into receive mode. Now the 1-Wire bus is pulled to VPUP through the pullup resistor. When the threshold VTH is crossed, the DS28E02 waits and then transmits a presence pulse by pulling the line low. To detect a presence pulse, the master must test the logical state of the 1-Wire line at tMSP. pulling the data line low; its internal timing generator determines when this pulldown ends and the voltage starts rising again. When responding with a 1, the DS28E02 does not hold the data line low at all, and the voltage starts rising as soon as tRL is over. The sum of tRL + (rise time) on one side and the internal timing generator of the DS28E02 on the other side define the master sampling window (t MSRMIN to tMSRMAX), in which the master must perform a read from the data line. For the most reliable communication, tRL should be as short as permissible, and the master should read close to but no later than tMSRMAX. After reading from the data line, the master must wait until tSLOT is expired. This guarantees sufficient recovery time tREC for the DS28E02 to get ready for the next time slot. Note that tREC specified herein applies only to a single DS28E02 attached to a 1-Wire line. For multidevice configurations, tREC must be extended to accommodate the additional 1-Wire device input capacitance.
DS28E02
Read/Write Time Slots
Data communication with the DS28E02 takes place in time slots that carry a single bit each. Write time slots transport data from bus master to slave. Read time slots transfer data from slave to master. Figure 12 illustrates the definitions of the write and read time slots. All communication begins with the master pulling the data line low. As the voltage on the 1-Wire line falls below the threshold VTL, the DS28E02 starts its internal timing generator that determines when the data line is sampled during a write time slot and how long data is valid during a read time slot.
Improved Network Behavior (Switchpoint Hysteresis)
In a 1-Wire environment, line termination is possible only during transients controlled by the bus master (1-Wire driver). 1-Wire networks, therefore, are susceptible to noise of various origins. Depending on the physical size and topology of the network, reflections from end points and branch points can add up or cancel each other to some extent. Such reflections are visible as glitches or ringing on the 1-Wire communication line. Noise coupled onto the 1-Wire line from external sources can also result in signal glitching. A glitch during the rising edge of a time slot can cause a slave device to lose synchronization with the master and, consequently, result in a Search ROM command coming to a dead end or cause a device-specific function command to abort. For better performance in network applications, the DS28E02 uses a new 1-Wire front-end, which makes it less sensitive to noise. The DS28E02's 1-Wire front-end differs from traditional slave devices in two characteristics. 1) There is additional lowpass filtering in the circuit that detects the falling edge at the beginning of a time slot. This reduces the sensitivity to high-frequency noise. This additional filtering does not apply at overdrive speed. 2) There is a hysteresis at the low-to-high switching threshold VTH. If a negative glitch crosses VTH but does not go below VTH - VHY, it is not recognized (Figure 13). The hysteresis is effective at any 1-Wire speed.
Master-to-Slave
For a write-one time slot, the voltage on the data line must have crossed the VTH threshold before the writeone low time tW1LMAX is expired. For a write-zero time slot, the voltage on the data line must stay below the VTH threshold until the write-zero low time tW0LMIN is expired. For the most reliable communication, the voltage on the data line should not exceed VILMAX during the entire tW0L or tW1L window. After the VTH threshold has been crossed, the DS28E02 needs a recovery time tREC before it is ready for the next time slot.
Slave-to-Master A read-data time slot begins like a write-one time slot. The voltage on the data line must remain below VTL until the read low time tRL is expired. During the tRL window, when responding with a 0, the DS28E02 starts
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1-Wire SHA-1 Authenticated 1Kb EEPROM with 1.8V Operation DS28E02
WRITE-ONE TIME SLOT tW1L VPUP VIHMASTER VTH VTL VILMAX 0V tF
tSLOT RESISTOR MASTER
WRITE-ZERO TIME SLOT tW0L VPUP VIHMASTER VTH VTL VILMAX 0V tF tSLOT RESISTOR MASTER
tREC
READ-DATA TIME SLOT tMSR tRL VPUP VIHMASTER VTH VTL VILMAX 0V tF
MASTER SAMPLING WINDOW tSLOT RESISTOR MASTER DS28E02
tREC
Figure 12. Read/Write Timing Diagrams
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1-Wire SHA-1 Authenticated 1Kb EEPROM with 1.8V Operation DS28E02
CRC Generation
The DS28E02 uses two different types of CRCs. One CRC is an 8-bit type that is computed at the factory and is stored in the most significant byte of the 64-bit registration number. The bus master can compute a CRC value from the first 56 bits of the 64-bit registration number and compare it to the value read from the DS28E02 to determine if the registration number has been received error-free. The equivalent polynomial function of this CRC is X 8 + X 5 + X 4 + 1. This 8-bit CRC is received in the true (noninverted) form. The other CRC is a 16-bit type, which is used for error detection with memory and SHA-1 commands. For details, refer to the full data sheet.
VPUP VTH
VHY
0V
Figure 13. Noise Suppression Scheme
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1-Wire SHA-1 Authenticated 1Kb EEPROM with 1.8V Operation DS28E02
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE 6 TSOC 6 TDFN-EP PACKAGE CODE D6+1 T633+2 DOCUMENT NO. 21-0382 21-0137 ______________________________________________________________________________________ 33
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1-Wire SHA-1 Authenticated 1Kb EEPROM with 1.8V Operation DS28E02
Revision History
REVISION NUMBER 0 REVISION DATE 6/10 Initial release DESCRIPTION PAGES CHANGED --
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
34 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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